| ISBN: ISBN: 0-7695-2827-9
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| ISBN: ISSN: 1530-1877
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| ISBN: DOI: 10.1109/ETS.2007.10
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| |
| description |
An efficient on-chip infrastructure for memory test and repair is
crucial to enhance yield and availability of SoCs. A commonly used
repair strategy is to equip memories with spare rows and columns (2D
redundancy). Although exact algorithms are available for offline
repair analysis, they cannot be directly applied on-chip because of
the prohibitive storage requirements for failture bitmaps and the
complex data structures inherent in the algorithms. Existing
heuristics for built-in repair analysis (BIRA) try to circumvent
this problem either by very simple search strategies or by
restricting the search to smaller local bitmaps. Exact BIRA
algorithms work with sub analyzers for each possible repair
combination. While a parallel implementation suffers from a high
hardware overhead, a serial implementation leads to high test times.
The integrated built-in test and repair approach proposed in this
paper interleaves test and repair analysis and supports an exact
solution without failure bitmap. The search can be implemented with
a stack, which is limited by the number of redundant elements. The
basic search procedure is combined with an efficient technique to
continuously reduce the problem complexity and keep the test and
analysis time low.
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| publisher |
Institute of Electrical and Electronics Engineers
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| type |
Text
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| Article in Proceedings
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| source |
In: 12th IEEE European Test Symposium (ETS), Freiburg, Germany, May
21-24, 2007, pp. 91-96
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| contributor |
ITI, Rechnerarchitektur
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| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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